The present invention relates to computer memory arrays. More particularly, the present invention relates to a method for mapping non-functional locations of random access memory array chips, such as audio DRAM chips, so that the chips may thereafter be used within a computer memory storage subsystem for storing digitized voice messages and facsimile data.
Computer systems following conventional architectures include a central processing unit (CPU) and main memory array which is used to store the application's and operating system's control programs which are executed by the CPU. A bus structure enables the CPU and main memory array to receive and send data to peripheral equipment, such as input/output (I/O) devices and auxiliary data storage and retrieval devices such as disk drives.
One type conventional memory array commonly used is the dynamic random access memory or DRAM. DRAM technology has progressed to the point where single DRAM chips may provide as much as a megabit or four megabits, or more, of storage. For example, an array of eight one megabit chips provides a megabyte of data storage capacity while an array of 16 one megabit chips provides a megaword of data storage capacity. Larger capacity chips provide even greater storage capacities. In order to assure integrity of each bit position within a particular address location, several approaches have been followed. The simplest approach is a single additional parity bit position which checks the parity (odd or even) of the particular byte or word to be stored at the address and indicates an error if, as actually stored, the parity is different than anticipated.
Another approach is to provide an error correction scheme which requires as many as six extra bit positions for a 16 bit word. One example of such approach is provided by the Nagano, et al. U.S. Pat. No. 4,394,763. This patent describes a method for detecting two-bit errors with an error correction code (ECC) scheme and then swapping a spare bit storage cell in place of a suspected defective cell and rerunning the bus memory transfer cycle. If only a single error remains, the ECC corrects this error and the process continues. In other words, the Nagano, et al. approach is to provide dynamic bit swapping within an ECC scheme in order to replace bad bit cells with substitute good bit cells during operation of the memory array. The evident drawback of the Nagano, et al. approach is that the ECC scheme requires considerable overhead in order to provide a six bit error correction code value for each sixteen bit word.
Another technique suggested by the prior art in Beausoleil U.S. Pat. No. 3,644,902 is to provide a mechanism for physically reconfiguring the boards comprising a memory array, so that an arrangement of boards in which a data word has a two bit error is changed to a new arrangement wherein a single bit error remains. Then, conventional ECC techniques may be used to correct for the single bit error.
DRAM chips are typically specified as having certain electrical characteristics. For computer service, characteristics such as power consumption, access times (speed), refresh rate, and freedom from nonfunctional storage locations are considered to be critical. Unfortunately, the manufacturing process is not yet sufficiently reliable in the megabit capacity ranges to provide full yields of chips that meet or exceed specifications relating to these four characteristics. However, a significant number of chips are produced which meet a slightly relaxed or less stringent set of specifications.
Since these chips cannot be reliably used within computer main memory, they are available at significantly lower cost than chips which meet the more stringent specifications for use within main memory of a digital computer. Other applications having relaxed specifications have been proposed and found for these chips. Such applications typically utilize fault tolerant data, which is binary data such as, for example, digitized audio information which can tolerate a few faulty bits within the data without seriously corrupting the data as a whole. Since these partially defective memory chips are mostly used within digital audio voice recording systems, wherein single bit or several bit non-functionality will not perceptibly degrade reconstituted audio information, these chips have come to be known within the semiconductor industry as "AUDIO DRAM" or ARAM.
However, for obvious reasons, ARAM chips have not conventionally been used for storage of fault non-tolerant data, which is binary data such as, for example, computer program code or facsimile data which cannot tolerate any faulty bits within the data. A hitherto unsolved need has arisen for the practical utilization of Audio DRAM within computing systems in order to realize a low cost, high storage capacity solid state memory array.
It is therefore an objective of the present invention to provide a memory management technique for allowing ARAM chips to be utilized for storage of both fault tolerant binary data and fault non-tolerant binary data.